1. Field of the Invention
The present invention relates to a capacitor and a capacitor array, and more particularly to a capacitor and a capacitor array capable of reducing an affection of parasitic capacitance.
2. Description of the Related Art
A metal oxide semiconductor (MOS) process provides a good quality oxide layer. Here, precision capacitors can be manufactured by using the good quality oxide layers. The precision capacitors constitute a capacitor array in a configuration of a binary-weighted ladder, and the capacitor array can be used in an analog-to-digital converter (ADC), a digital-to-analog converter (DAC), a filter, and so on.
A ratio matching is of great importance in the capacitors constituting the capacitor array. However, a ratio error between the capacitors results from the limitations of the manufacturing process. The ratio errors result from an edge definition error in a masking process, a thickness gradient of the oxide layer, a parasitic capacitance caused by metal lines formed on the oxide layers, and a parasitic capacitance caused by metal lines connecting the capacitors and each element.
FIGS. 1A through 1D are diagrams illustrating conventional capacitor arrays.
Referring to FIG. 1A, capacitors 110, 111 and 112 constitute a capacitor array of binary-weighted ladder type. The capacitors 110, 111 and 112, respectively, have capacitances 4C1, 2C1 and C1, and have different areas.
The capacitor 110 has an area four times larger than the area of the capacitor 112. The capacitor 111 has an area two times larger than the area of the capacitor 112. However, an area ratio of the capacitors 110, 111 and 112 is not exactly 4:2:1 because of the edge definition errors. Therefore, the approach for making a capacitor array of binary-weighted ladder shown in FIG. 1A cannot be used in precise ADCs or DACs, which adjust the capacitance by the area ratios of the capacitors.
FIG. 1B illustrates a capacitor array of a binary-weighted ladder type that eliminates the edge definition error. The capacitor array includes a plurality of unit capacitors 120 through 127 having the same areas and structures. The capacitance of the unit capacitor corresponds to C1. In this case, a required capacitance is obtained by connecting the plurality of unit capacitors 120 through 127 to each other. For example, when the capacitors 120, 121, 124 and 125 are connected, the capacitance of the connected capacitors 120, 121, 124 and 125 corresponds to 4C1. When the capacitors 122 and 126 are connected, the capacitance of the connected capacitors 122 and 126 corresponds to 2C1. The capacitance of the capacitor 127 corresponds to C1. These capacitors 120 through 127 constitute a capacitor array that provides a 4:2:1 capacitance ratio. The capacitor array in FIG. 1B eliminates the edge definition error by using the unit capacitor, but has a precision limitation caused by the thickness of the oxide layers. That is, the capacitor 120 and the capacitor 127 can have different thicknesses of the oxide layers because of the thickness gradient of the oxide layers. Thus, the capacitors 120 and 127 have different capacitances.
FIG. 1C illustrates a conventional capacitor array that reduces errors caused by the thickness gradient of the oxide layers. The capacitor array is also referred to as a capacitor array of a common centroid type. When capacitors 130 through 138 are connected to obtain a required capacitance, the capacitors 130 through 138 are connected symmetrically to the center of the capacitor array. For example, when the capacitors 130, 132, 136 and 138 are connected, the capacitance of the connected capacitors 130, 132, 136 and 138 corresponds to 4C1. When the capacitors 131 and 137 are connected, the capacitance of the connected capacitors 131 and 137 corresponds to 2C1. The capacitance of capacitor 134 corresponds to C1. These capacitors 130 through 137 constitute a capacitor array that provides a 4:2:1 capacitance ratio.
Recently, more precise capacitors have been manufactured owing to a development of the MOS process technology. In addition, as an area of the unit capacitor is decreased, the capacitance of the unit capacitor is decreased. Therefore, a problem of the parasitic capacitance occurs more frequently. For example, the thickness gradient of the oxide layers is scarcely problematic in the capacitor array of the common centroid type in FIG. 1C. However, more parasitic capacitances occur, for example, between the lines connecting the unit capacitors with a small capacitance and the unit capacitors, and between the unit capacitors, in comparison with the capacitance of the unit capacitor. Thus, the capacitor array of the common centroid type cannot be readily adapted for large-scaled integrated ADCs or DACs.
FIG. 1D illustrates a capacitor array disclosed in Korean Patent Laid-Open Publication No. 1999-001795. The capacitors 140 through 146 constituting the capacitor array are arranged in a row at identical intervals in the same direction. The capacitor array in FIG. 1D is less affected by the parasitic capacitance caused by the metal lines, owing to simply arranging the capacitors in a row. In addition, by connecting 4 or 2 capacitors symmetrically to the center, there is a reduced influence of the gradient of the thickness of the oxide layers. However, a straight-typed capacitor array as shown in FIG. 1D is not readily adapted to being manufactured with a large number capacitors.